1. Field of the Invention
This Invention relates to a nonvolatile semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device which internally has a function of verifying whether or not writing or erasure has been performed completely.
2. Description of the Related Art
An electrically reloadable read only memory device (hereinafter referred to as EEPROM) has an erasure mode in which stored information in memory cells are erased, and particularly, a memory device which can be electrically reloaded in a flash (hereinafter referred to as flash EEPROM) generally has an automatic erasure function of erasing stored information by internal control.
In a flash EEPROM having an automatic erasure function, an erasure operation is divided into an erasure period in which a high voltage is applied to memory cells and a subsequent period in which it is verified whether or not the memory cells are read out after completion of the erasure period to verify whether or not the threshold levels of them have become lower than a preset value. During the erasure period, the flash EEPROM is controlled by pulses (erasure signal) of several ms to several hundreds ms generated internally therein, but during the verification period, the flash EEPROM is controlled by pulses (verify signal) of several hundreds ns to several tens is generated internally therein.
In particular, in an erasure operation, stored information of the memory cells is erased actually when the erasure signal is at a high ("H") level, and then, after the erasure signal changes to a low ("L") level and the verify signal changes to the "H" level, a read circuit is activated to effect verification. If the result of erasure is incomplete, then the erasure signal changes to the "H" level to effect erasure of the memory cells again, and thereafter, verification is performed again. Then, such erasure of the memory cells is repeated until it is determined as a result of verification that erasure has been performed completely.
FIG. 7 schematically shows a portion of a conventional flash EEPROM to which the present invention is directed. Referring to FIG. 7, the circuit portion shown has an external power source terminal CC, an external ground terminal GND, an external VPP power source terminal PP to which a voltage higher than the power source voltage is applied upon writing or erasure, and an output terminal 0 from which stored information is outputted externally.
The flash EEPROM includes memory cells M.sub.11 to M.sub.nm having a floating gate structure and arranged in a matrix of m columns and n rows. N-channel enhancement type MOSFETs (Metal-Oxide Semiconductor Field Effect Transistors) (hereinafter referred to as NE-MOSFETs) QY.sub.1 to QY.sub.m for selecting a Y address for the memory cells and connecting the drain of the thus selected memory cell to an an input node SC of a sense amplifier circuit SA, Y address lines Y.sub.1 to Y.sub.m for designating a Y address for the memory cells, X address lines X.sub.1 to X.sub.n for designating an X address for the memory cells, a signal line RD which provides, in a read mode in which stored information of the memory cells is read out and upon verification, the "H" level to activate associated circuits, another signal line Erase which provides the "H" level for an erasure period, and a further signal line Veri which provides the "H" level upon verification. The flash EEPROM further includes the sense amplifier circuit SA, a reference circuit REF, a comparator detector DA for comparing the voltage of the output SO of the sense amplifier circuit SA with the voltage of the output RO of the reference circuit REF and amplifying a difference between the voltages, an output buffer circuit OUT for transmitting the output DO of the comparator detector DA to the output terminal O, and a coincidence detection circuit COMP for comparing the logic values of the output DO of the comparator detector DA and a signal DATA with each other to detect whether or not erasure of a memory cell has been completed.
The coincidence detection circuit COMP is controlled by the signal Veri such that it is activated when the signal Veri changes, upon verification, to the "H" level so that the logic values of the output DO and the signal DATA are compared with each other. When the logic values coincide with each other, the coincidence detection circuit COMP outputs, for example, the "L" level at the output CO thereof, but when the logic values do not coincide with each other, the coincidence detection circuit COMP outputs the "H" level.
The output CO is inputted to a circuit (not shown) which determines whether not erasure should be ended finally. The circuit fetches data of the output CO at a certain timing, and if the level of the output CO is the "L" level, it determines that the memory cells have been erased completely and ends the erasure, but if the level of the output CO Is the "H" level, then it determines that the memory cells have not been erased completely and accordingly generates an erasure signal again. Consequently, another erasure period is started to effect erasure of the memory cells.
A source switch circuit SW sets a potential to a source line CS common to the memory cells. When the erasure period signal Erase changes to the "H" level, the source switch circuit SW is activated so that a high voltage is applied to the source line CS. Consequently, all of the memory cells connected to the source line CS are erased. On the other hand, in a read mode or upon verification, the source switch circuit SW sets the potential to the source line CS to zero volt.
A parasitic inductance component L.sub.cc originating from leads of a package is present between the external power source terminal CC and an internal power source line, and a similar parasitic inductance component L.sub.ss is present between the external ground terminal GND and an internal grounding line. Resistors shown in FIG. 7 are parasitic resistance components originating from resistances of aluminum lines of the individual circuits wired to the power source and the ground. Further, a capacitance component Ce originating from a capacitance of a diffused layer and so forth appears between the internal power source and the ground. When those components need originally be represented in a distributed constant network, they are shown as seen in FIG. 7 for simplified illustration.
An actual flash EEPROM includes, where it has an 8-bit output configuration, eight such circuits as shown in FIG. 7. However, only one such circuit is shown in FIG. 7 for simplified illustration.
Operation of the flash EEPROM upon erasure will be described below with reference to FIGS. 9 to 13. In the flash EEPROM, writing of all bits of the memory cells is performed In order to make the threshold levels of the memory cells uniform before erasure. In this instance, the threshold levels of the memory cells are raised to a sufficiently high voltage normally equal to or higher than 7 volts.
Thereafter, an erasure operation is started. In the erasure operation, a high voltage is applied to the source line CS common to the memory cells, whereupon electrons which were injected into the floating gates during the preceding writing operation, are discharged to the sources. Consequently, the threshold level of each memory cell drops in accordance with the extent of the erasure period.
FIG. 8 illustrates the variation of the threshold level V.sub.TM of a memory cell with respect to the integrated time t.sub.pe of the erasure period. Referring to FIG. 8, for example, after t.sub.pe5 after application of a first erasure pulse, the threshold level of the memory cell varies to V.sub.TM5, and then, verification is performed and it is determined that erasure is incomplete. Thus, after t.sub.pe5, within which several erasure pulses are applied, the threshold level of the memory cell changes to V.sub.TM4.
Upon verification, the individual memory cells are read by the sense amplifier circuit SA. It is assumed that, in the present example, a memory cell which has written information therein (that is, a memory cell from which information has not been erased completely) has "O" stored therein, and when the memory cell is read, the "H" level appears at the output DO of the comparator detector DA, whereas another cell which has been erased completely has "1" stored therein, and when the memory cell is read, the "L" level appears at the output DO of the comparator detector DA.
Upon verification, the flash EEPROM is generally controlled such that a voltage of approximately 4.0 volts is applied to a selected X address line (for example, X.sub.1). This is because, in a read mode, a memory cell with which it is determined that information has been erased completely as a result of verification must be read stably within an allowable power source voltage range (from 4.5 volts to 5.5 volts).
The verification operation is performed reading out information of all of the memory cells from which information has been erased in a flash. In particular, the flash EEPROM includes an internal counter (not shown) for counting an address, and in the example of FIG. 7, it is determined from a count value of the counter whether or not erasure of all of the memory cells M.sub.11 to M.sub.nm has been performed completely. If it is determined during such verification that erasure is incomplete, then the verification is stopped, and an erasure pulse is generated to perform another erasure operation. If is is finally determined that all of the memory cells have been erased completely, it is determined that the intended erasure is completed, and the erasure operation is ended.
FIG. 9 shows a curve K which illustrates the relationship of the electric current I.sub.on (cell) flowing through a memory cell to the threshold level V.sub.TM of the memory cell upon verification and another curve L which illustrates the relationship the output voltage V.sub.SO of the sense amplifier SA to the current I.sub.ON (cell).
When erasure of a memory cell proceeds, the threshold level V.sub.TM with respect to the erasure time exhibits such a variation as seen in FIG. 8, and as a result, the current flowing through the selected memory cell varies In accordance with the curve Kin FIG. 9 and the output voltage V.sub.SO of the sense amplifier circuit SA varies in accordance with the curve L in FIG. 9.
For example, at the time when the integrated time of erasure is t.sub.pe3, the memory cell has a threshold level V.sub.TM =V.sub.TM3 =3.5 volts, and the current I.sub.ON (cell) flowing through the memory cell then is given at a point K.sub.1 as seen in FIG. 9, at which I.sub.ON (cell)=10 .mu.A. As a result, the output voltage V.sub.SO of the sense amplifier SA is given at a point L.sub.1, at which V.sub.SO1 =3.4 volts.
When the erasure integrated time is t.sub.pe1, the memory cell has a threshold level V.sub.TM =V.sub.TM1 =3.0 volts, and in this instance, the current I.sub.ON (cell) is given at a point K.sub.2, at which I.sub.ON (cell)=20 .mu.A. As a result, the output voltage V.sub.SO of the sense amplifier circuit SA is given at a point L.sub.2, at which V.sub.SO2 =3.0 volts.
In FIG. 9, the value represented by V.sub.REF indicates the output voltage of the reference circuit REF and provides a point for determination whether a selected memory cell should be considered to be in a written condition ("0") in which information is stored in the memory cell or in an erased condition ("1") in which no information is stored in the memory cell. In the example shown, the output voltage V.sub.REF is set to V.sub.REF =3.2 volts.
It is to be noted that, in FIG. 9, reference character A.sub.1 denotes a "1" detection region, A.sub.2 a transition region (in which detection is impossible), and A.sub.3 a "0" detection region.
FIG. 10 shows an exemplary construction of the comparator detector DA which compares the output voltage V.sub.SO of the sense amplifier SA and the output voltage V.sub.REF of the reference circuit REF with each other and amplifies a difference between them. FIG. 11 illustrates the input/output characteristic of the comparator detector DA. Referring to FIGS. 10 and 11, the comparator detector DA shown includes a pair of P-channel enhancement type MOSFETs (hereinafter referred to as PE-MOSFETs) Q.sub.D1 and Q.sub.D2, three NE-MOSFETs Q.sub.D3, Q.sub.D4 and Q.sub.D5, and an inverter circuit INV. A signal line RD provides the "H" level in a read mode and upon verification, and the comparator detector DA is activated by the "H" level of the signal line RD.
The comparator detector DA is generally designed such that, when the output voltage V.sub.SO of the sense amplifier circuit SA becomes equal to the output voltage V.sub.REF of the reference circuit REF, that is, V.sub.SO =V.sub.REF, the voltage V.sub.D1 at a node D.sub.1 and the voltage V.sub.D2 at another node D.sub.2 become equal to each other and the value of the voltages then makes a logic threshold level of the inverter circuit INV. In other words, the logic threshold level of the comparator detector DA is given when V.sub.SO =V.sub.REF. Accordingly, ideally it is detected that a selected memory cell is in a written condition when the value of the output voltage V.sub.SO satisfies the following expression (1) whereas it is detected that the selected memory cell is in a completely erased condition when the value of the output voltage V.sub.SO satisfies the following expression (2): EQU V.sub.SO &gt;V.sub.REF ( 1) EQU V.sub.SO &lt;V.sub.REF ( 2)
In an actual flash EEPROM, however, since the parasitic Inductances L.sub.cc and L.sub.ss, the parasitic capacitance between the power source and the ground and the parasitic resistance between a power source line and a grounding line are involved as seen from FIG. 7, noise originating from switching of a MOSFET and so forth is generated upon verification, and the comparator detector DA cannot have characteristics of ideal conditions represented by the expressions (1) and (2), but when the value of the output voltage V.sub.SO is in the proximity of the output voltage V.sub.REF as seen from FIG. 11, an output indefinite region is present in which the output DO of the comparator detector DA exhibits an oscillation condition.
Accordingly, actually it is detected that a selected memory cell is in a written condition when the value of the output voltage V.sub.SO satisfies the following expression (3) whereas it is detected that a selected memory cell is in an erased condition when the value of the output voltage V.sub.SO satisfies the following expression (4): EQU V.sub.SO .gtoreq.V.sub.REF+.alpha. ( 3) EQU V.sub.SO .ltoreq.V.sub.REF-.beta. ( 4)
where .alpha. and .beta. are noise margins of the output voltage V.sub.SO to the output voltage V.sub.REF necessary for the output DO to be detected as at the "H" level.
On the other hand, when the value of the output V.sub.SO satisfies the following expression (5), it is impossible to definitely determine the condition of the selected memory cell: EQU V.sub.REF -.beta.&lt;V.sub.SO &lt;V.sub.REF+.alpha. ( 5)
It is to be noted that the following description proceeds on the assumption that .alpha.=.beta.=0.2 volts.
The conventional flash EEPROM performs its erasure operation in such a manner as described above, and as seen in FIG. 8, when the integrated time of the erasure period is t.sub.pe3, the threshold level of the selected memory cell is V.sub.TM =V.sub.TM3 =3.5 volts, and when verification is performed then, the value of the output voltage V.sub.SO varies, as seen from FIG. 9, to V.sub.SO =V.sub.SO1 =3.4 volts. Thus, if V.sub.REF =3.2 volts, then the expression (3) is satisfied. Consequently, it is determined that erasure is not yet complete, and another erasure period is set to further erase the memory cell.
In this instance, when the integrated time of the erasure period comes to t.sub.pe2, the threshold level V.sub.TM becomes V.sub.TM =V.sub.TM2 =3.2 volts. Thus, upon verification, the value of the electric current I.sub.ON (cell) is obtained at a point K.sub.3 of the curve K in FIG. 9, and the value of the output V.sub.SO is obtained at a point L.sub.3 of the curve L in FIG. 9 and V.sub.SO =V.sub.SO3 =3.15 volts. In this instance, since the value of the output V.sub.SO satisfies the expression (5), as seen from the characteristic In FIG. 11, the value of the output V.sub.SO is within the output indefinite region and the output DO of the comparator detector DA enters such an oscillation condition as seen in FIG. 13(B).
It is to be noted that FIGS. 13(A) to 13(C) show output waveforms of the two components upon verification in an erasure operation where the integrated time t.sub.pe of the erasure period is in the ranges of t.sub.pe .ltoreq.t.sub.pe3, t.sub.pe3 &lt;t.sub.pe &lt;t.sub.pe1, and t.sub.pe .gtoreq.t.sub.pe1, respectively.
FIG. 12 shows an exemplary construction of the coincidence detection circuit COMP. Referring to FIG. 12, the coincidence detection circuit COMP includes PE-MOSFETs Q.sub.C1, Q.sub.C3, Q.sub.C5, Q.sub.C7, Q.sub.C9 and Q.sub.C11 and NE-MOSFETs Q.sub.C2, Q.sub.C4, Q.sub.C6, Q.sub.C8, Q.sub.C10 and Q.sub.C12, which cooperatively constitute an exclusive OR circuit. The coincidence detection circuit COMP is activated upon verification to logically exclusively OR the output DO of the comparator detector DA and the signal DATA.
Consequently, the voltage variation of the output CO directly reflects the voltage variation of the output DO, and when the value of the output V.sub.SO enters the output indefinite region, the output CO exhibits an oscillation condition as seen from FIG. 13(B) similarly to the output DO.
In this instance, if the circuit which determines whether or not erasure should be ended finally fetches the data of the output CO at the time t.sub.1 in FIGS. 13(A) to 13(C), it will determine that the erasure should be ended since the level of the output CO is "L" although the logic value of the output CO is indefinite and the output is in an oscillation condition, and as a result, the erasure will be ended although erasure of the memory cell is not complete as yet. In other words, no erasure signal is generated, and the erasure operation for the memory cell is not performed any more.
As described above, in the present case, in order to allow it to be detected that a memory cell has been erased completely, the value of the output V.sub.SO must satisfy the expression (4), and if V.sub.REF =3.2 volts and .beta.=0.2 volts, then the output V.sub.SO .ltoreq.3.0 volts is necessary. Reading the value of the threshold level V.sub.TM corresponding to the output V.sub.SO .ltoreq.3.0 volts from FIG. 9, the threshold level V.sub.TM .ltoreq.3.0 volts is necessary. In other words, if the threshold level V.sub.TM of the memory cell is not V.sub.TM =V.sub.TMC =3.0 volts or less upon verification after an erasure period, then it is not determined that the memory cell has been erased completely.
Since the value of the output V.sub.SO with which the comparator detector DA falls in the output indefinite region is obtained from the expression (5) as described above, in the present case, if .alpha.=.beta.=0.2 volts and V.sub.REF =3.2 volts, then 3.0 volts &lt;V.sub.TM &lt;3.4 volts. Reading the value of the threshold level V.sub.TM corresponding to it from FIG. 9, 3.0 volts &lt;V.sub.TM &lt;3.5 volts. Thus, when the value of the threshold level V.sub.TM is within the range upon verification after an erasure period, the comparator detector DA cannot definitely determine whether stored information of the memory cell is "0" or "1", and the output DO of the comparator detector DA exhibits an oscillation condition. Consequently, also the output CO of the coincidence detection circuit COMP exhibits an oscillation condition, and if the data of the output CO are fetched at the position of t.sub.1 In FIG. 13, then the erasure is ended.
In this instance, since the threshold level of the memory cell has not yet dropped below a preset value (in the present example, V.sub.TM =3.0 volts), even if stored information of the memory cell is read out in a read mode, the memory cell current I.sub.ON (cell) is lower than its originally designed value. This results in reduction of the reading speed or disabling of information "0" stored originally in the memory cells, giving rise to a problem of malfunctioning of the flash EEPROM.
As described above, in a conventional flash EEPROM, when the threshold level of a memory cell is, upon verification after an erasure period in an erasure operation for the memory cell, within a transition region (detection disable region) In which it is indefinite whether a comparator detector detects information of the memory cell as "1" or "0", the output of the comparator detector exhibits oscillations, and since the output of the comparator detector is inputted directly to a coincidence detection circuit for detecting whether or not the erasure Is completed, if the output of the comparator detector oscillates, also the output of the coincidence detection circuit oscillates. Accordingly, the conventional flash EEPROM has a problem in that, although erasure is not sufficient, such oscillation condition is determined to be completion of erasure and the erasure is ended in error.
Consequently, the reading speed in a read mode is retarded or stored information of memory cells cannot be read out correctly, and the reliability of the conventional flash EEPROM is not sufficiently high.